1. Field of the Invention
The present invention relates to an MCM (multichip module) into which a plurality of semiconductor devices are merged, and to semiconductor devices to be used in the MCM.
2. Description of the Related Art
As electronic apparatuses grow more miniaturized and sophisticated, miniaturization and sophistication are also demanded of semiconductor devices to be mounted on the electronic apparatuses. On this account, system LSIs capable of constituting a system on a single chip and MCMs, or LSI packages on which a plurality of bare chips are mounted, have been developed. Recently, there have been developed MCMs called chip-on-chip, or LSI chips having other LSI chips layered thereon.
For example, in the cases of merging logic chips and memory chips to manufacture MCMs, the logic chips and the memory chips are individually completed through different wafer processes. The completed logic chips and memory chips are individually subjected to probe tests for good-die screening before the dicing of the chips on the wafers. Then, only the good dies are used to assemble MCMs.
In general, logic chips to be mounted on MCMs have a control circuit for controlling a memory chip, and an interface circuit to the memory chip. No memory chip is connected, however, at the occasion of the probe tests on the logic chips. Accordingly, there has been a problem that the probe tests cannot involve operation tests on the above-mentioned control circuit and interface circuit.
For example, in the cases where data to be processed in functional blocks on a logic chip is temporarily stored in a memory chip (or when the memory chip is used as a buffer), it is impossible to evaluate the passing of data between the functional blocks and the memory chip, and between the functional blocks.
Conventionally, the operation tests and evaluations mentioned above could not be made until logic chips and memory chips were assembled into MCMs. Therefore, in case where a control circuit or an interface circuit was defective in an assembled MCM, the assembled MCM had to be discarded as a defective even though it contained a good memory chip.
It is an object of the invention to surely perform tests independently on a semiconductor device to be used for MCMs before the MCM assembly.
It is another object of the invention to improve the assembly yield of the MCM.
According to one of the aspects of the semiconductor device and multichip module in the present invention, a semiconductor memory device manufactured separately is connected to an interface unit of the semiconductor device. An internal memory formed in the semiconductor device is connected to at least a part of the interface unit. A memory selecting circuit makes the internal memory accessible in a first operation mode, and makes the internal memory inaccessible in a second operation mode. Therefore, for example, putting the semiconductor device into the first operation mode and accessing the internal memory allows the semiconductor device to be operated as a predetermined system even when the semiconductor memory device is not connected to the interface unit. The substitution of the internal memory for the semiconductor memory device makes it possible for the semiconductor device to test the interface unit and associated circuits thereof alone, by itself. This consequently allows improvement in the assembly yield of the multichip module. When the internal memory is used for the tests, the internal memory may have a memory capacity smaller than that of the semiconductor memory device.
After the semiconductor device and the semiconductor memory device are connected via the interface unit (assembled into a multichip module), the semiconductor device can make access to the internal memory in the first operation mode and make access to the semiconductor memory device in the second operation mode to increase the memory capacity available. For example, forming a terminal for transmitting the information that indicates the first operation mode or the second operation mode to the semiconductor memory device facilitates the switching of accesses between the internal memory and the semiconductor memory device.
According to another aspect of the semiconductor device and multichip module in the present invention, at least a part of the interface unit is shared between the internal memory and the semiconductor memory device. On this account, the semiconductor device can make access to the internal memory and the semiconductor memory device with the interface unit minimized in circuit scale. Accessing the semiconductor memory device in the second operation mode will not cause any conflicts in the data bus or the like.
According to another aspect of the semiconductor device and multichip module in the present invention, the interface unit includes a first interface unit and a second interface unit. The first interface unit is connected to the internal memory, and outputs a control signal when in the first operation mode. Here, the semiconductor device can make access to the internal memory. The second interface unit is connected to the semiconductor memory device, and outputs a control signal when in the second operation mode. Here, the semiconductor device can make access to the semiconductor memory device. The semiconductor device controlling the first and second interface units in accordance with its operation mode facilitates the access to the internal memory and the semiconductor memory device.
According to another aspect of the semiconductor device in the present invention, the first interface unit outputs to the internal memory a first selecting signal which is activated upon access to the internal memory. The second interface circuit outputs to the semiconductor memory device a second selecting signal which is activated upon access to the semiconductor memory device. The memory selecting circuit activates the first interface unit in the first operation mode to operate the internal memory, and activates the second interface unit in the second operation mode to operate the semiconductor memory device. Thus, the semiconductor device activating the first and second interface units in accordance with its operation mode facilitates the access to the internal memory and the semiconductor memory device.
According to another aspect of the semiconductor device and multichip module in the present invention, the semiconductor device enters the first operation mode (test mode) in performing tests, and enters the second operation mode (normal operation mode) in operating the semiconductor memory device. Executing operation tests by using the internal memory facilitates the determination as to whether a defect originates in the semiconductor device or the semiconductor memory device. Moreover, the substitution of the internal memory for the semiconductor memory device makes it possible for the semiconductor device to test the interface unit and associated circuits thereof by itself before the semiconductor memory device is connected to the interface unit.
According to another aspect of the semiconductor device in the present invention, memory elements of the internal memory are different in type from those of the semiconductor memory device. A conversion circuit of the internal memory converts the timing of outputting a control signal of the semiconductor memory device from the interface unit into timing for operating the internal memory. By virtue of the conversion circuit, the internal memory operates as if it is the semiconductor memory device. That is, the internal memory imitatively makes the same operation as that of the semiconductor memory device. Forming the internal memory with memory cells of a simpler manufacturing process allows a reduction in the chip size of the semiconductor device. For example, when the semiconductor memory device is constituted as a DRAM, the internal memory may be formed as an SRAM.
According to another aspect of the semiconductor device in the present invention, the interface unit can judge whether or not a refresh controlling signal is transmitted properly, even when the internal memory is composed of static memory elements. That is, operation tests of the control circuit for generating the refresh controlling signal and the interface unit on the semiconductor device can be performed by the semiconductor device alone.